1. Field of the Invention
The present invention relates to a monitor, and more particularly to a frame size regulating circuit of a monitor for regulating a frame size in accordance with a picture brightness signal and pulsewidth modulation signals to thereby provide high picture quality to a viewer.
2. Description of the Prior Art
In a television set or a monitor, generally, a vertical sync signal ("synchronization" is abbreviated as "sync") and a horizontal sync signal are supplied to a deflection circuit which in turn oscillates the vertical sync signal and horizontal sync signal to provide a vertical deflection signal of a triangular waveform and a horizontal deflection signal of a square waveform. The vertical deflection signal of the triangular waveform is applied to a convergence coil and a vertical deflection yoke, and the horizontal deflection signal of the square waveform is applied to the convergence coil, a horizontal deflection yoke and a flyback transformer.
The convergence coil generates a uniform magnetic field for maintaining a convergence of electron beams which is supplied to the frontal plane of a CRT (Cathode Ray Tube) screen, deflecting the electron beams in the horizontal and the vertical direction in the vertical and the horizontal deflection yoke, and maintaining convergence and purity. The flyback transformer produces a high voltage required for the CRT.
Once the high voltage produced from the flyback transformer ascends over a preset value, the rectilinear motion of the electron beams is reinforced. Thus, the electron beams collide against the frontal plane of the CRT prior to being fully deflected to reduce the frame size. However, if the high voltage descends below the preset value, the deflecting action of the electron beams is reinforced to enlarge the frame size.
A frame size regulating circuit for correcting the varied frame size resulting from the fluctuation of the high voltage is illustrated in FIG. 1.
In FIG. 1, a reference numeral 1 denotes a microprocessor for generating pulsewidth modulation signals PWM1 and PWM2 having varied duties in accordance with horizontal and vertical sync signals Hs and Vs, and a reference numeral 2 is a horizontal-size control signal generator part for generating a horizontal size control signal of DC component for regulating the horizontal size in accordance with pulsewidth modulation signal PWM1. A reference numeral 3 denotes a horizontal size control signal part for overlapping the horizontal size control with an externally-provided distortion correction signal GD, and regulating the horizontal size by an overlap signal obtained. A reference numeral 4 denotes a vertical-size control signal generator part for generating a vertical size control signal of DC component for regulating the vertical size in accordance with pulsewidth modulation signal PWM2, and a reference numeral 5 is a deflection circuit for producing a vertical deflection signal of triangular waveform in accordance with the vertical size control signal and externally-provided vertical sync signal Vs.
Horizontal-size control signal generator part 2 is illustrated in FIG. 2. Here, horizontal-size control signal generator part 3 includes an amplifier for amplifying a DC voltage obtained by shaping pulsewidth modulation signal PWM1, and resistors 22 and 24 connected to the (-) port of amplifier 20 and an output side of amplifier 20 for determining the amplification factor of the DC voltage. In addition to these, a plurality of resistors 10, 12, 14 and 18 and a capacitor 16 are connected to the (+) port of amplifier 20 for overlapping pulsewidth modulation signal PWM1 with a division signal of a DC power source Vcc to provide a DC voltage.
Referring to FIG. 2, the connection of plurality of resistors 10, 12, 14 and 18 and capacitor 16 will be considered. An output side of microprocessor 1 is connected with one port of resistor 10 which biases pulsewidth modulation signal PWM1, and the other side of resistor 10 is connected to output sides of resistors 12 and 14 for dividing externally-supplied power source Vcc. The other side of resistor 14 is grounded. The other side of resistor 10 and output side of resistor 12 are connected to each other, and the output side of resistor 12 is connected to one side of capacitor 16 for smoothing the overlap signal of the division voltage of resistors 12 and 14, and the other side of capacitor 16 is grounded. One side of capacitor 16 is connected to one side of resistor 18 for biasing an output voltage of capacitor 16, and the other side of resistor 18 is connected to the (+) port of amplifier 20.
Meanwhile, vertical-size control signal generator part 4 is constructed to be identical to horizontal-size control signal generator part 2.
In the above-described conventional frame size regulating circuit, an operation of horizontal-size control signal generator circuit 2 will be described first. Pulsewidth modulation signal PWM1 of microprocessor 1 is supplied to resistor 10 of horizontal-size control signal generator circuit 2, and resistor 10 biases pulsewidth modulation signal PWM1. Externally-supplied power source Vcc is supplied to resistors 12 and 14 which then divide power source Vcc, and the bias voltage of resistor 10 and division voltages of resistors 12 and 14 overlap with each other.
The overlap signal is supplied to capacitor 16 which smooths the overlap signal to provide a first DC voltage. Then, the first DC voltage is supplied to amplifier 20 to be amplified. At this time, the amplification factor of amplifier 20 is determined in association with resistors 22 and 24. Here, the amplified DC voltage is the horizontal size control signal which is provided to be approximately 4.95 V when the horizontal size is maximum and to be approximately 10.56 V when the horizontal size is minimum.
The horizontal size control signal of horizontal-size control signal generator part 2 is supplied to horizontal size control part 3. Then, horizontal size control part 3 overlaps the horizontal size control signal with distortion correction signal GD supplied from an microcomputer(not shown), and supplies the overlap signal to an diode modulation(not shown).
On the other hand, vertical-size control signal generator part 4 is operated to be identical to horizontal-size control signal generator part 2 to provide the vertical size control signal of DC component. The vertical size control signal is supplied to deflection circuit 5. In deflection circuit 5, the vertical deflection signal of triangular waveform is generated in accordance with the vertical size control signal and vertical sync signal.
However, in the conventional monitor, the number of electron beams is varied in accordance with the brightness of an image. Also, once the number of electron beams is varied, the frame size is varied as well. In other words, when the image is brightened, the number of electron beams is increased to increase the current flowing to the flyback transformer to increase overall amount of the current. Then, the high voltage is lowered to enlarge the frame size.
In the event that such conventional frame size regulating circuit is employed, the frame size is varied as many as approximately 6 mm when the high voltage is fluctuated within the range of about 24 KV to 25 KV. In other words, the frame size is severely varied due to the change of the brightness of image to involve a drawback of degrading picture quality.